FIG. 9 shows a configuration of a typical liquid crystal display system. In FIG. 9, an LCD (Liquid Crystal Display) panel is omitted, and a driver circuit for driving gate lines (scan lines) of the LCD panel, its power supply circuit, and a driving clock system are illustrated.
The typical liquid crystal display system includes an oscillation circuit 11 for generating a reference clock signal CLK (osc) for the display system, a display counter circuit 12 for generating a reference clock signal CLK (drv) for selecting a gate line, a driver circuit 13 for driving the gate lines (scan lines) of the LCD panel, a frequency divider circuit 14 for generating a clock signal CLK (dcdc) for a boost circuit 15, and the boost circuit 15 for supplying a power for a display driver. The frequency of the reference clock signal CLK (osc) is indicated by Fosc, the frequency of the line selection reference clock signal CLK (drv) is indicated by Fdrv, and the frequency of the boost operation clock signal CLK (dcdc) is indicated by Fdcdc. In the LCD panel, each gate line is connected in common to the gates of a plurality of pixel transistors (TFTs) for one line.
An operation of the liquid crystal display system shown in FIG. 9 is as follows:
The oscillation circuit 11 generates the reference clock signal CLK (osc) of the predetermined frequency Fosc, and supplies the reference clock signal CLK (osc) to the display counter circuit 12 and the frequency divider circuit 14.
The display counter circuit 12 divides the frequency of the input reference clock signal CLK (osc) by n, where n is a predetermined positive integer, to generate the line selection reference clock signal CLK (drv) for supplying the the line selection reference clock signal CLK (drv) to the driver circuit 13. The frequency Fdrv of the line selection reference clock signal CLK (drv) is equal to Fosc/n.
The frequency divider circuit 14 supplies the clock signal CLK (dcdc) obtained on dividing the frequency of the reference clock signal CLK (osc) by m to the boost circuit 15 as the boost operation clock signal CLK (dcdc) for controlling a boost operation. The frequency Fdcdc of the boost operation clock signal CLK (dcdc) equals to Fosc/m.
The boost circuit 15 performs the boost operation in synchronization with the clock signal CLK (dcdc) to supply the boosted voltage as a power supply voltage to the driver circuit 13.
FIG. 12 is a diagram for explaining the operation principle of the boost circuit 15 (which is a DC/DC converter). The boost circuit shown in FIG. 12 outputs from an output terminal DCDCout a voltage (2×VDD) which has been boosted to twice a reference power supply (VDD). The boost circuit includes a switch S1 having one terminal thereof connected to the power supply VDD, a charging capacitor C1 having one terminal thereof connected to the other terminal of the switch S1, a switch S3 having one terminal thereof connected to the power supply VDD and the other terminal thereof connected to the other terminal of the charging capacitor C1, a switch S2 connected between the other terminal of the charging capacitor C1 and a ground GND, a switch 4 having one terminal thereof connected to the one terminal of the charging capacitor C1 and the other terminal thereof connected to the output terminal DCDCout, and a smoothing capacitor C2 connected between the output terminal DCDCout and the ground GND.
FIG. 13 is a timing diagram showing an example of ON (conducting) and OFF (non-conducting) operations of the switches S1 to S4 in FIG. 12. As shown in FIG. 13, the switches S1 to S4 repeat ON and OFF operations in synchronization with the boost operation clock signal CLK (dcdc), thereby causing the boost circuit 15 to repeat charging and discharging periods to generate a boosted voltage. When the switches S1 and S2 are turned ON and the switches S3 and S4 are turned OFF, the charging capacitor C1 is charged, and the voltage of the output terminal DCDCout falls in response to discharging (a predetermined time constant) of the smoothing capacitor C2. When the switches S1 and S2 are turned OFF and switches S3 and S4 are turned ON, one terminal of the charging capacitor C1 is connected to the output terminal DCDCout and the other terminal of the charging capacitor C1 is connected to the supply voltage VDD. Thus, a boosted voltage in which the voltage across the terminals of the charging capacitor C1 is added to the supply voltage VDD is output to the output terminal DCDCout. The output voltage DCDCout of the boost circuit 15 has ripples synchronized with charging and discharging periods, as shown in FIG. 13. These ripples follows two conditions below described.
The resistance values of the switches S1 to S4 are zero.
The load current of the boost circuit is constant.
A configuration is known in which the switches S1 to S4 are constituted from thin-film transistors (TFTs), and a horizontal shift clock or a vertical shift clock for scanning a gate electrode is input to a frequency divider circuit as a DC/DC converter for supplying power to the gate electrode driver circuit of the LCD panel (refer to Patent Document 1 to be described hereinafter).
[Patent Document 1]
JP Patent Kokai JP-P2001-183702A (p. 5, FIG. 4, FIG. 5)